1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device (synchronous memory) which operates synchronously with an externally input signal, and more particularly to a synchronous memory which outputs a data strobe signal and delivers output data synchronously with the data strobe signal so as to facilitate the construction of a high-speed semiconductor memory system.
2. Description of the Related Art
Usually, a semiconductor integrated circuit (LSI circuit) receives an external signal as an input and produces an output signal by performing operations appropriate to the input signal. The timing at which the output signal will be obtained in response to the external input signal is important; for general purpose LSIs, such timing is usually defined in their specifications. For example, for dynamic random access memories (DRAMs), the timing for data output relative to a changing edge of an address signal and the data setup time required to write data are specified along with the maximum frequency of the address signal, etc.
In recent years, with increasing CPU clock speeds in computer systems, or with increasing processing speeds of various electronic circuits, it has become imperative to develop higher-speed interfaces. For example, CPUs with 100 MHz or higher clock speeds are available, but compared with the CPU speeds, the access speed and data transfer speed of DRAM widely used as main memory are an order of magnitude slower. To address this situation, a variety of DRAM systems such as synchronous DRAM (SDRAM) have been proposed that achieve data transfer rates of 100 MHz or higher.
The SDRAM performs data input/output operations synchronously with an externally input high-speed clock, and incorporates a plurality of units to enable multi-bit data to be input and output in parallel. High-speed interfacing with an external device is achieved by a method in which the multi-bit data are converted into serial data, or by a method in which internal operations are pipelined and the operations in the pipes are carried out in parallel, or by a combination of these two methods.
Traditional SDRAMs operate synchronously with a clock CLK supplied from a controller, and when writing data to SDRAM, the write data is latched into the SDRAM by operating its latch circuit for latching the write data or address sent from the controller, synchronously with the received clock. Likewise, when reading data from SDRAM, the read data is output from the SDRAM by operating its data output circuit for outputting data read out of an internal memory cell, synchronously with the received CLK. The signals sent from the controller to the SDRAM do not pose any problems since they are sent along substantially the same signal path as the CLK and therefore, a phase shift (skew) with respect to the CLK can be minimized, but a problem can arise when sending readout data from the SDRAM to the controller; that is, even if the SDRAM outputs the data synchronously with the received CLK, since the data is sent in the opposite direction to the CLK, there occurs a skew between the CLK and the readout data by the time the data is received at the controller. Such a skew has not been much of a problem for previous SDRAMs having relatively slow operating speeds, but this skew cannot be ignored when constructing a memory system using an SDRAM operating at a speed higher than 100 MHz. In view of this problem, it has been proposed to have the SDRAM output a data strobe signal DS and deliver readout data synchronously with this DS. The above skew problem can be alleviated by configuring the controller to operate its readout data latch circuit synchronously with the received DS and thereby latch the data into the controller.
However, the skew cannot be eliminated completely since actually there exist slight differences in wiring and also differences between wiring patterns for multi-bit data DQ. Furthermore, the pulse used to latch data into the data latch circuit must be provided with a minimum required width, and there also exist differences in the layout of the plurality of multi-bit data lines within the controller, in wiring length, and even in leadframe length. All of these factors contribute to increasing the skew. On top of that, when a delay circuit is used in the controller, not only manufacturing variations among chips but differences in temperature and supply voltage also cause variations. Overall, a large margin has to be allowed, and this determines the limit of the operating speed of SDRAM. Therefore, to achieve a high-speed SDRAM, this operating margin must be reduced.